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1 6-channel led driver with ultra low dimming capability isl97672a the isl97672a is an integrated 6-channel power led driver for lcd backlight applications. the isl97672a is capable of driving leds with input from 4.5v to 26.5v and maximum output up to 45v. the isl97672a employs an adaptive boost switching architecture that allows dire ct pwm dimming with dimming duty cycle as low as 0.007% at 200hz or 0.8% at 20khz. pwm dimming frequency can be as high as 30khz. the isl97672a employs the dynamic headroom control that monitors the highest led forwar d voltage string for output regulation to minimize headroom voltage and power loss in a typical multi-string operation. typical current matching between channels is 0.7%. the isl97672a incorporates extensive protection functions that flag whenever a fault occurs. the protections include string-open and short-circuit detections, ovp, otp, and an optional output short-circuit pr otection with external fault disconnect switch. the isl97672a is offered in a compact 20 ld qfn 3x4 package and can operate in ambient temperatures of -40c to +85c. features ?6 x 50ma channels ? 4.5v to 26.5v input ? 45v output max ? adaptive boost switching architecture ? direct pwm dimming with dimming linearity of 0.007%~100% at 200hz or 0.8%~100% <20khz ? adjustable 200khz to 1.4mhz switching frequency ? dynamic headroom control ? fault protections with latched flag indication -string open/short circuit -ovp -otp - optional output short-circuit fault protection switch ? current matching 0.7% ? 20 ld 3x4 qfn package applications ? notebook displays led backlighting ? lcd monitor led backlighting ? multi-function printer scanning light source typical application circuit figure 1. isl97672a typical application diagram flag v in = 4.5~26.5v comp vin ovp pwm v out = 45v*, 6 x 50ma vdc ch0 ch3 ch2 ch4 ch5 rset 2 4 6 18 5 17 15 14 13 12 11 10 16 lx 20 pgnd 19 agnd 9 isl97672a ch1 en 3 *v in > 12v fault 1 q1(optional) fsw 8 november 22, 2013 fn7710.3 n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a rt i s l 9 7 6 7 2 b caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2011, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl97672a 2 fn7710.3 november 22, 2013 block diagram pin configuration isl97672a (20 ld 3x4 qfn) top view figure 2. isl97672a block diagram + - + - + - + - 45v*, 6x50ma ovp pgnd ch0 ch1 ch5 *v in 12v 5 fault flag 0 pwm5 pwm1 pwm0 open ckt, short ckt detects fet driver highest vf string detect vset ref gen dimming controller osc & ramp comp fault 10h/1.5a en vdc flag comp rset gnd pwm reg v in = 4.5v~26.5v vin bias f sw fault flag boost sw 4.7f/50v lx ref_vsc ref_ovp sensor temp fault/status control logic ilimit imax fault flag = 0 (optional q1) gm amp o/p short ovp ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # isl97672airz 672a 20 ld 3x4 qfn l20.3x4 ISL97672AIRZ-EVALZ evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tech brief tb347 for details on reel specifications. 2. these intersil pb-free plastic pack aged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-fr ee products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl97672a . for more information on msl, please see tech brief tb363 . lx pgnd comp rset nc fsw agnd ch0 fault vin en vdc pwm /flag ovp ch5 ch4 ch3 ch2 ch1 1 2 3 4 5 6 16 15 14 13 12 11 20 19 18 17 78910
isl97672a 3 fn7710.3 november 22, 2013 pin descriptions (i = input, o = output, s = supply) pin name pin # type description fault 1 o a pull-down current output for exte rnal p-channel fault disconnect switch. vin 2 s input supply voltage for ic. connect a 0.1f decoupling capacitor close to this pin. en 3 i ic enable pin. pull high to enable the ic. if en is low for lo nger than 30.5ms, ic will be disabled. vdc 4 s internal 5v regulator. connect a 1f decoupling capacitor on vdc. pwm 5 i pwm input pin for direct pwm dimming control. /flag 6 o /flag is latched low under any fault condition and resets after input power is recycled or part is re-enabled. this pin is an open drain that needs pull-up. nc 7 i no connect. fsw 8 i boost switching frequency set pin. connect a resistor be tween this pin and ground to set up desired boost switching frequency. see ?switching frequency? on page 9 for resistance calculation. agnd 9 s analog ground for precision circuits. ch0, ch1 ch2, ch3 ch4, ch5 10, 11, 12, 13, 14, 15 i current source and channel monitoring input for channel 0, 1, 2 3, 4, 5. ovp 16 i overvoltage protection input. see ?ovp and v out ? section on page 10. rset 17 i led dc current set pin. connect a resistor between this pin and ground to set up maximum led dc current. see ?maximum dc current setting? on page 9 for resistance calculation. comp 18 o boost compensation pin. connect an rc compensati on network between this pin and gnd to optimize boost stability and transient response. pgnd 19 s power ground. lx 20 o boost converter switching node.
isl97672a 4 fn7710.3 november 22, 2013 absolute maximum ratings (t a = +25c) thermal information vin, en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vin - 8.5v to vin + 0.3v vdc, comp, rset, pwm, ovp, fsw . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v ch0 - ch5, lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 45v pgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v note: voltage ratings are with respect to agnd pin. esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 300v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv thermal resistance (typical) ja (c/w) jc (c/w) 20 ld qfn package (notes 4, 5, 7) . . . . . . 40 2.5 thermal characterization (typical) psi jt (c/w) 20 ld qfn package (note 6) . . . . . . . . . . . . . . . . . . . . . 1 maximum continuous junction temperature . . . . . . . . . . . . . . . . .+125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb347 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. psi jt is the junction-to-top thermal resistance. if the package top te mperature can be measured, with this rating then the die junct ion temperature can be estimated more accurately than the ja and jc thermal resistance ratings. 7. refer to jesd51-7 high effective thermal conducti vity board layout for proper via and plane designs. electrical specifications all specifications are tested at t a = +25c, v in = 12v, en = 5v, r set = 20.5k , unless otherwise noted. boldface limits apply over the operating juncti on temperature range, -40c to +85c. parameter description condition min (note 8) typ max (note 8) unit general v in (note 10) vin supply voltage t c = <+60c t a = +25c 4.5 26.5 v ivin vin current en = 5v 5 ma ivin_stby vin shutdown current t a = +25c 5 a v out output voltage 4.5v < v in 26v, f sw = 600khz 45 v 8.55v < v in 26v, f sw = 1.2mhz 45 v 4.5v < v in 8.55v, f sw =1.2mhz v in /0.19 v v uvlo undervoltage lock-out threshold 2.1 2.6 v v uvlo_hys undervoltage lock-out hysteresis 200 mv enable and pwm generator v il guaranteed range for pwm input low voltage 0.8 v v ih guaranteed range for pwm input high voltage 1.5 vdd v fpwm pwm input frequency range 200 30,000 hz t on minimum on time 250 350 ns
isl97672a 5 fn7710.3 november 22, 2013 regulator vdc ldo output voltage v in > 6v 4.55 4.8 5 v ivdc_stby standby current en = 0v 5 a vldo vdc ldo droop voltage v in > 5.5v, 20ma 20 200 mv en low guaranteed range for en input low voltage 0.5 v en hi guaranteed range for en input high voltage 1.8 v t enlow en low time before shut-down 30.5 ms boost sw ilimit boost fet current limit 1.5 2.0 2.7 a r ds(on) internal boost switch on-resistance t a = +25c 235 300 m ? ss boost soft-start time 100% led duty cycle 7 ms eff_peak peak efficiency v in = 12v, 72 leds, 20ma each, l = 10h with dcr 101m ? , t a = +25c 92.9 % v in = 12v, 60 leds, 20ma each, l = 10h with dcr 101m ? , t a = +25c 90.8 % i out / v in line regulation 0.1 % d max boost maximum duty cycle f sw = 600khz 90 % f sw = 1.2mhz 81 % d min boost minimum duty cycle f sw = 600khz 9.5 % f sw = 1.2mhz 17 % f s minimum switching frequency r fsw = 200k ? 175 200 235 khz f s maximum switching frequency r fsw = 33k ? 1.312 1.50 1.69 mhz i lx_leakage lx leakage current lx = 45v, en = 0 10 a current sources i match channel-to-channel current matching r set =20.5k ? (i out = 20ma) 0.7 1.0 % i acc current accuracy -1.5 +1.5 % v headroom20 dominant channel current source headroom at iin pin measured with i led = 20ma i led = 20ma t a = +25c 500 (note 9) mv v headroom33 dominant channel current source headroom at iin pin measured with i led = 33ma i led = 33ma t a = +25c 560 (note 9) 710 860 (note 9) v rset voltage at rset pin r set = 20.5k ? 1.2 1.22 1.24 v i ledmax maximum led current per channel v in = 12v, v out = 45v, f sw = 1.2mhz, t a = +25c 50 ma fault detection vsc channel short circuit threshold pwm dimming = 100% 7.5 8.2 v temp_shtdwn over-temperature shutdown threshold 150 c temp_hyst over-temperature shutdown hysteresis 23 c vovplo overvoltage limit on ovp pin 1.199 1.24 v electrical specifications all specifications are tested at t a = +25c, v in = 12v, en = 5v, r set = 20.5k , unless otherwise noted. boldface limits apply over the operating juncti on temperature range, -40c to +85c. parameter description condition min (note 8) typ max (note 8) unit
isl97672a 6 fn7710.3 november 22, 2013 flag_on flag voltage when fault occurs when fault occurs, i pullup= 4ma 0.04 0.12 v fault pin i fault fault pull-down current v in = 12v 12 21 30 a v fault fault clamp voltage with respect to v in v in = 12, v in - v fault 6 7 8.3 v lxstart_thres lx start-up threshold 0.9 1.2 v ilx startup lx start-up current vdc = 5.0v 1 3.5 5 ma notes: 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 9. compliance to limits is assure d by characterization and design. 10. at maximum v in of 26.5v, minimum v out is 28v. minimum v out can be lower at lower v in . electrical specifications all specifications are tested at t a = +25c, v in = 12v, en = 5v, r set = 20.5k , unless otherwise noted. boldface limits apply over the operating juncti on temperature range, -40c to +85c. parameter description condition min (note 8) typ max (note 8) unit typical performance curves figure 3. efficiency vs up to 20ma led current (100% led duty cycle) vs v in figure 4. efficiency vs up to 30ma led current (100% led duty cycle) vs v in figure 5. efficiency vs v in vs switching frequency at 20ma (100% led duty cycle) figure 6. efficiency vs v in vs switching frequency at 30ma (100% led duty cycle) 100 70 80 90 50 30 40 60 0 10 20 0 5 10 15 20 25 efficiency (%) i led(ma) 5v in 12v in 24v in 100 70 80 90 50 30 40 60 0 10 20 0 5 10 15 20 25 efficiency (%) i led(ma) 30 35 6p10s_30ma/channel 5v in 12v in 24v in 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 1.2mhz 580k efficiency (%) v in 0 5 10 15 20 25 efficiency (%) v in 30 1.2mhz 0 20 40 60 80 100 580k
isl97672a 7 fn7710.3 november 22, 2013 figure 7. efficiency vs v in vs temperature at 20ma (100% led duty cycle) figure 8. channel-to-channel current matching figure 9. current linearity vs low level pwm dimming duty cycle vs v in figure 10. v headroom vs v in vs temperature at 20ma figure 11. v out ripple voltage, v in = 12v, 6p12s at 20ma/channel figure 12. start up waveforms at v in = 6v for 6p12s at 20ma/channel typical performance curves (continued) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 +25c -40c 0c +85c efficiency (%) v in 0.40 0.10 0.20 0.30 -0.10 -0.20 0.00 012345 current matching (%) channel 6 -0.30 -0.40 7 21 v in 12 v in 4.5 v in 0 0.2 0.4 0.6 0.8 1.0 1.2 01 4 pwm dimming duty cycle (%) 23 56 current(ma) 4.5 v in 12 v in 0.40 0.45 0.50 0.55 0.60 0 5 10 15 20 25 30 v headroom (v) -40c 0c +25c v in (v) 2.00s/div v o = 50mv/div v_out v_en v_lx i_inductor v_out v_en v_lx i_inductor
isl97672a 8 fn7710.3 november 22, 2013 figure 13. startup waveforms at v in = 12v for 6p12s at 20ma/channel figure 14. line regulation with v in change from 6v to 26v, 6p12s at 20ma/channel figure 15. line regulation with v in change from 26v to 6v for 6p12s at 20ma/channel figure 16. boost output voltage with brightness change from 0% to 100%, v in = 12v, 6p12s at 20ma/channel figure 17. boost output voltage with brightness change from 100% to 0%, v in = 12v, 6p12s at 20ma/channel figure 18. isl97672a shuts down and stops switching ~30ms after en goes low typical performance curves (continued) i_inductor v_out v_en v_lx v_out v_en v_lx i_inductor 6p12s, 20ma/ch v in = 10v/div 10.0ms/div i_v in = 1a/div iled = 20ma/div en 6p12s, 20ma/ch v in = 10v/div 10.0ms/div i_v in = 1a/div iled = 20ma/div en 6p12s, 20ma/ch v o = 1v/div 10.0ms/div iled = 20ma/div 6p12s, 20ma/ch v o = 1v/div 10.0ms/div iled = 20ma/div 6p12s, 20ma/ch v o = 10v/div 20.0ms/div i_v in = 1a/div iled = 20ma/div en
isl97672a 9 fn7710.3 november 22, 2013 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the isl97672a employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. such architecture achieves a fast transient response that is essential for notebook backlight applications in which drained batteries can be instantly changed to an ac/dc adapter without noticeable visual disturbance. th e number of leds that can be driven by isl97672a depends on the type of led chosen in the application. the isl97672a is capable of boosting up to 45v and typically driving 13 leds in series for each of the 6 channels, enabling a total of 78 pieces of the 3.2v/20ma type of leds. enable device is enabled if the enable pin voltage is high. if en is pulled low for longer than 30.5ms, the device will be shutdown. the enable pin should not float, a 10k or high er pull-down resistor should be connected between en and gnd. current matching and current accuracy each channel of the led current is regulated by the current source circuit, as shown in figure 19. the led dc current is set by translating the r set current to the output, with a scaling factor of 410.5/r set . the source terminals of the current source mosfets ar e designed to run at 500mv to optimize power loss versus accura cy requirements. the sources of errors of the channel-to-channel current matching come from the op amp?s offset, internal layout, reference and current source resistors. these parameters are optimized for current matching and absolute current accuracy. the absolute accuracy is also affected by the external r set . a 1% tolerance resistor should be used. dynamic headroom control the isl97672a features a pr oprietary dynamic headroom control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the ch0 through ch5 pins. when this lowest channel voltage is lower than the short-circuit threshold, v sc , this voltage is used as the feedback signal for the boost regulator. th e boost adjusts the output to the correct level such that the lowest channel pin is at the target headroom voltage. since all le d stacks are connected to the same output voltage, the other ch annel pins will have a higher voltage, but the regulated current source circuit on each channel ensures that each channel has the same current. the output voltage regulates cycle by cycle, and it is always referenced to the highest forward voltage string in the architecture. dimming controls the isl97672a allows two ways of controlling the led current, and therefore, the brightness. they are: 1. dc current adjustment 2. pwm chopping of the led current defined in step 1. maximum dc current setting the led dc current of each channel can be calculated as shown in equation 1: for example, if the maximum required led current (i led(max) ) is 20ma, rearranging equation 1 yields equation 2: pwm current control the isl97672a employs direct pwm dimming such that the output pwm dimming follows directly with the input pwm signal without modifying the input frequency. the average led current of each channel can be calculated as shown in equation 3: switching frequency the boost switching frequency can be adjusted by connecting a resistor between the fsw pin and gnd. the calculation of the resistance is shown in equation 4: where f sw is the desirable boost switching frequency, and r fsw is the setting resistor. 5v low dropout regulator there is an internal 5v low dropout (ldo) regulator to develop the necessary low-voltage supply, which is used by the chip?s internal control circuitry. vdc is the outp ut of this ldo regulator which requires a bypass capacitor of 1f or more for the regulation. the vdc pin can be used as a coarse reference as long as it is sourcing only a few milliamps. + - + - ref rset pwm dimming + - dc dimming figure 19. simplified current source circuit i ledmax 410.5 r set --------------- = (eq. 1) r set 410.5 0.02 ? 20.52k == (eq. 2) i led ave () i led pwm = (eq. 3) f sw 5 10 10 () r fsw ----------------------- = (eq. 4)
isl97672a 10 fn7710.3 november 22, 2013 ic protection features and fault management isl97672a has several protection and fault management features that improve system re liability. the following sections describe them in more detail. in-rush control and soft-start the isl97672a has separate, built-in, independent in-rush control and soft-start functions. the in-rush control function is built around an external short-ci rcuit protection p-channel fet in series with vin. at start-up, the fault protection fet is turned on slowly due to a 21a pull-down current output from the fault pin. this discharges the fault fet's gate-source capacitance, turning on the fet in a controlled fashion. as this happens, the output capacitor is charged slowly through the low-current fet before it becomes fully enhanced. this results in a low in-rush current. this current can be further reduced by adding a capacitor (in the 1nf to 5nf range) across the gate source terminals of the fet. once the chip detects that the fault protection fet is turned on fully, it assumes that in-rush is complete. at this point, the boost regulator begins to switch, and the current in the inductor ramps up. the current in the boost power switch is monitored, and switching is terminated in any cycle in which the current exceeds the current limit. the isl97672a includes a soft-start feature in which this current limit starts at a low value (275ma). this value is stepped up to the final 2.2a current limit in seven additional steps of 275ma each. these steps happen over at least 8ms and are extended at low led pwm freque ncies if the led duty cycle is low. this extension allows the output capacitor to charge to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. for systems with no master fault protection fet, the in-rush current flows towards c out when v in is applied. the in-rush current is determined by the ramp rate of v in and the values of c out and l. fault protection and monitoring the isl97672a features extensive protection functions to cover all perceivable failure conditions. the /flag pin is a latched open-drain output that monito rs string open, led short, v out short, and overvoltage and over-t emperature conditions. this pin resets only when input power is recycled or the part is re-enabled. the failure mode of an led can be either an open circuit or a short. the behavior of an open -circuited led can additionally take the form of either infinite resistance or, for some leds, a zener diode, which is integrated into the device in parallel with the now-opened led. for basic leds (which do not ha ve built-in zener diodes), an open-circuit failure of an led results only in the loss of one channel of leds, without affecting other channels. similarly, a short-circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the isl97672a uses feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the led stacks to fault out. see table 1 for details. a fault condition that results in an input current that exceeds the device?s electrical limits will result in a shutdown of all output channels. short-circuit protection (scp) the short-circuit detection circui t monitors the voltage on each channel and disables faulty channels that are above approximately 7.5v (this action is described in table 1 on page 12). open-circuit protection (ocp) when one of the leds becomes an open circuit, it can behave as either an infinite resistance or as a gradually increasing finite resistance. the isl97672a monitors the current in each channel such that any string that reaches the intended output current is considered ?good.? should the cu rrent subsequently fall below the target, the channel is considered an ?open circuit.? furthermore, should the boost output of the isl97672a reach the ovp limit, or should the lower over-temperature threshold be reached, all channels that are not good are im mediately considered to be open circuit. detection of an open circuit channel results in a time-out before the affected channel is disabled. this time-out is sped up when the device is above the lower over-temperature threshold, in an attempt to prevent the upper over-temperature trip point from being reached. some users employ special types of leds that have a zener diode structure in parallel with the led. this configuration provides esd enhancement and enables open-circuit operation. when this type of led is open circuited, the effect is as if the led forward voltage has increased but the lighting level has not increased. any affected string will not be disabled, unless the failure results in the boost ovp limit being reached, which allows all other leds in the string to remain functional. in this case, care should be taken that the boost ovp limit and scp limit are set properly, to ensure that multiple failures on one string do not cause all other good channels to fault out. this condition could arise if the increased forward voltage of the faulty channel makes all other channels look as if they have led shorts. see table 1 for details of responses to fault conditions. ovp and v out the overvoltage protection (ovp) pi n has a function of setting the overvoltage trip level as well as limiting the v out regulation range. the isl97672a ovp threshold is set by r upper and r lower such that: and output voltage v out can regulate between 64% and 100% of the v out_ovp such that:? allowable v out = 64% to 100% of v out_ovp if, for example, 10 leds are used with the worst-case v out of 35v. v out_ovp 1.22vx r upper r lower + () r lower -------------------------------------------------------- = (eq. 5)
isl97672a 11 fn7710.3 november 22, 2013 if r 1 and r 2 are chosen such that the ovp level is set at 40v, then v out is allowed to operate between 25.6v and 40v. if the v out requirement is changed to an a pplication of six leds of 21v, then the ovp level must be reduced. users should follow the v out = (64% ~100%) ovp level requirement; otherwise, the headroom control will be disturbe d such that the channel voltage can be much higher than expected. this can sometimes prevent the driver from operating properly. the resistances should be large, to minimize power loss. for example, a 1m r upper and a 30k r lower sets ovp to 41.9v. large ovp resistors also allow c out to discharge slowly during the pwm off time. parallel capacitors should also be placed across the ovp resistors such that r upper /r lower = c lower /c upper . using a c upper value of 30pf is recommended. these capacitors reduce the ac impedance of the ovp node, which is important when using high-value resistors. for example, if r upper /r lower = 33/1, then c upper /c lower = 1/33 with c upper = 100pf and c lower =3.3nf undervoltage lock-out if the input voltage falls below th e uvlo level, the device stops switching and is reset. operation restarts only when v in returns to the normal operating range. input overcurrent protection during a normal switching operation, the current through the internal boost power fet is monitored. if the current exceeds the current limit, the internal switch is turned off. monitoring occurs on a cycle-by-cycle basis in a self-protecting way. additionally, the isl97672a monitors the voltage at the lx and ovp pins. at start- up, the lx pins inject a fixed current into the output capacitor. the device does not start unless the voltage at lx exceeds 1.2v. the ovp pin is also monitored su ch that if it rises above and subsequently falls below 20% of the target ovp level, the input protection fet is also switched off. over-temperature protection (otp) the isl97672a includes two over -temperature thresholds. the lower threshold is set to +130c. when this threshold is reached, any channel that is outputting curre nt at a level si gnificantly below the regulation target is treated as ?open circuit? and is disabled after a time-out period. this time-out period is 800s when it is above the lower threshold. the lower threshold isolates and disables bad channels before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. the upper threshold is set to +150c . each time this threshold is reached, the boost stops switching, and the output current sources switch off. once the devi ce has cooled to approximately +100c, the device restarts, with the dc led current level reduced to 75% of the initial setting. if dissipation persists, subsequent hitting of the limit causes identical behavior, with the current reduced in steps to 50% and finally 25%. unless disabled via the en pin, the device stays in an active state throughout. for complete details of fault protection conditions, see figure 20 and table 1. figure 20. simplified fault protections q5 vsc ch5 vset pwm/oc0/sc0 ref fet driver lx imax ilimit driver fault ovp vin t2 otp thrm shdn q0 vsc ch0 vout vset pwm/oc5/sc5 temp sensor logic lx t1 otp thrm shdn o/p short fault detect logic pwm generator fault flag /flag
isl97672a 12 fn7710.3 november 22, 2013 component selection according to the inductor voltage-second balance principle, the change of inductor current duri ng the switching regulator on time is equal to the change of inductor current during the switching regulator off time. as shown in equations 6 and 7, since the voltage across an inductor is: and i l @ on = i l @ off, therefore: where d is the switching duty cycle defined by the turn-on time over the switching period. v d is a schottky diode forward voltage that can be neglecte d for approximation. rearranging the terms without accounting for v d gives the boost ratio and duty cycle, respectively, as shown in equations 8 and 9: table 1. protections table case failure mode detection mode failed channel action good channel action v out regulated by 1chx short circuit upper over-temperature protection limit (otp) not triggered, and vchx < 7.5v chx on and burns power. remaining ch annels normal high est vf of all channels 2 chx short circuit upper otp triggered, but vchx < 7.5v all channels go off until chip cools, and then come back on with current reduced to 76%. subsequent otp triggers further reduce i out . same as chx highest vf of remaining channels 3 chx short circuit upper otp not triggered, but chx > 7.5v chx disabled after six pwm cycle time-outs. remaining channels normal highest vf of remaining channels 4 chx open circuit with infinite resistance upper otp not triggered, and chx < 7.5v v out ramps to ovp. chx times out after six pwm cycles and switches off. v out drops to normal level. remaining channels normal highest vf of remaining channels 5chx led open circuit but has paralleled zener upper otp not triggered, and chx < 7.5v chx remains on and has highest vf; thus, v out increases. remaining channels on, remaining channel fets burn power vf of chx 6chx led open circuit but has paralleled zener upper otp triggered, but chx < 7.5v all channels go off until chip cools, and then come back on with current reduced to 76%. subsequent otp triggers further reduce i out . same as chx vf of chx 7chx led open circuit but has paralleled zener upper otp not triggered, but chx > 7.5v chx remains on and has highest vf; thus, v out increases. v out increases, then chx switches off after six pwm cycles. this is an unwanted shut off and can be prevented by setting ovp at an appropriate level. vf of chx 8 channel-to-channel vf too high lower otp triggered, but chx< 7.5v any channel below the target current faults out after six pwm cycles. remaining channels are driv en with normal current. highest vf of remaining channels 9 channel-to-channel vf too high upper otp triggered, but chx < 7.5v all channels go off until chip cools and then come back on with current reduced to 75%. subsequent otp triggers further reduce i out . boost switches off 10 output led stack voltage too high v out > vovp any channel that is below the targ et current times out after six pwm cycles, and v out returns to normal regulation voltage required for other channels. highest vf of remaining channels 11 v out /lx shorted to gnd at start-up, or v out shorted in operation lx current and timing monitored. ovp pins monitored for excursions below 20% of ovp threshold. chip is permanently shut down 31ms after power-up if v out /lx is shorted to gnd. i l v l l ------ - x t = (eq. 6) v ( i 0 ) l ? dt s v o v d v i ? ? () = l1 ( d ) t s ? ? ? (eq. 7) v o v i 11d ? () ? = ? (eq. 8) dv o ( v i ) v o ? ? = (eq. 9)
isl97672a 13 fn7710.3 november 22, 2013 input capacitor switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. the capacitors reduce interaction between the regulator and input supply, thus improvin g system stability. the high switching frequency of the loop causes almost all ripple current to flow into the input capacitor, which must be rated accordingly. a capacitor with low internal seri es resistance should be chosen to minimize heating effects and to improve system efficiency. the x5r and x7r ceramic capacitors offer small size and a lower value for temperature and voltage coefficient compared to other ceramic capacitors. an input capacitor of 10f is recommended. ensure that the voltage rating of the input capacitor is able to handle the full supply range. inductor inductor selection should be based on its maximum current (i sat ) characteristics, power dissipati on (dcr), emi susceptibility (shielded vs unshielded), and size. inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance, and stability. inductor maximum current capability must be adequate to handle the peak current in the worst-case condition. if an inductor core with too low a current rating is chosen, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak-to-average current level, poor efficiency, and overheating in the core. the series resistance, dcr, within the inductor causes conduction loss and heat dissipation. a shielded inductor is usually more suitable for emi-susceptible applications such as led backlighting. the peak current can be derived from the voltage across the inductor during the off period, as shown in equation 10: the value of 85% is an average term for the efficiency approximation. the first term is average current that is inversely proportional to the input voltage. the second term is inductor current change that is inversely proportional to l and f s . as a result, for a given switching frequency and minimum input voltage at which the system operates, the inductor i sat must be chosen carefully. output capacitors the output capacitor smooths the output voltage and supplies load current directly during th e conduction phase of the power switch. output ripple voltage consists of discharge and charge of the output capacitor during fet on and off time and the voltage drop due to flow through the esr of the output capacitor. the ripple voltage can be shown as equation 11: the conservation of charge prin ciple shown in equation 9 also indicates that, during the boost switch off period, the output capacitor is charged with the inductor ripple current, minus a relatively small output current in boost topology. as a result, the user must select an output capa citor with low esr and adequate input ripple current capability. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. c out in equation 11 assumes the ef fective value of the capacitor at a particular voltage and not the manufacturer?s stated value, measured at 0v. the value of v co can be reduced by increasing c o or f s , or by using small esr capacitors. in general, ceramic capacitors are the best choice for output capacitors in small- to medium-sized lcd backlight applications, due to their cost, form factor, and low esr. a larger output capacitor also ea ses driver response during the pwm dimming off period, due to the longer sample and hold effect of the output drooping. the driver does not need to boost harder in the next on period that minimizes transient current. the output capacitor is also needed for compensation, and in general, 2x4.7f/50v ceramic capacitors are suitable for notebook display backlight applications. schottky diode a high-speed rectifier diode is necessary to prevent excessive voltage overshoot. schottky diodes are recommended because of their fast recovery time, low forward voltage and reverse leakage current, which minimize losses. the reverse voltage rating of the selected schottky diode must be higher than the maximum output voltage. also the average/peak current rating of the schottky diode must meet the output current and peak inductor current requirements. applications high-current applications each channel of the isl97672a can support up to 30ma (50ma @ v in = 12v). for applications th at need higher current, multiple channels can be grouped to achieve the desired current (figure 21). for example, the cathode of the last led can be connected to ch0 through ch2; this configuration can be treated as a single string with 90ma current driving capability. il peak v o ( i o ) 85% ( v i ) 12v i v o ( v i ) l ( v o f s ) ? ? [] ? + ? = (eq. 10) v co i ( o c o df s ) i ( o esr () + ? ? = (eq. 11) ch0 ch1 ch2 v out figure 21. grouping multiple channels for high current applications
isl97672a 14 fn7710.3 november 22, 2013 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/product_tree low-voltage operations the isl97672a vin pin can be separately biased from the led power input to allow low-voltage operation. for systems that have only a single supply, v out can be tied to the driver vin pin to allow initial start-up (figure 22). the circuit works as follows: when the input voltage is available and the device is not enabled, v out follows v in with a schottky diode voltage drop. the v out boot-strapped to the vin pin allows initial start-up, once the part is enabled. once the driver starts up with v out regulating to the target, the vin pin voltage also increases. as long as v out does not exceed 26.5v and the extra power loss on v in is acceptable, this configuration can be used fo r input voltage as low as 3.0v. the fault protection fet feature cannot be used in this configuration. for systems that have dual suppl ies, the vin pin can be biased from 5v to 12v, while input voltage can be as low as 2.7v (figure 23). in this configuration, vbias must be greater than or equal to vin to use the fault fet. compensation the isl97672a incorporates a tran sconductance amplifier in its feedback path to allow the user to optimize boost stability and transient response. the isl97672a uses current mode control architecture, which has a fast current sense loop and a slow voltage feedback loop. the fast current feedback loop does not require any compensation, but fo r stable operation, the slow voltage loop must be compensated. the compensation is a series of rc, cc1 network from comp pin to ground, with an optional cc2 capacitor connected between the comp pin and ground. the rc sets the high-frequency integrator gain for fast transient response, and the cc1 sets the integrator zero to ensure loop stability. for most applications, the component values in figure 24 can be used: rc is 10k ? and cc1 is 3.3nf. depending upon the pcb layout, for stability, a cc2 of 390pf may be needed to create a pole to cancel the output capacitor esr?s zero effect. v in = 3v~21v flag pwm comp vin ovp rset vdc ch0 ch3 ch2 ch4 ch5 fsw 2 4 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97672a ch1 en 3 26.5v*, 6 x 50ma fault 1 *v in > 12v figure 22. single supply 3.0v operation v in = 2.7~26.5v 45v*, 6 x 50ma *v in > 12v flag pwm comp vin ovp rset vdc ch0 ch3 ch2 ch4 ch5 fsw 2 4 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97672a ch1 en 3 vbias = 5v~12v fault 1 q1 (optional) figure 23. dual supply 2.7v operation rc 10k cc1 3.3nf cc2 390pf comp figure 24. compensation circuit
isl97672a 15 fn7710.3 november 22, 2013 about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change september 19, 2012 fn7710.3 1. vovplo limits changed to [1.199vmin, 1.24vmax] in electrical specification table. 2. ovp lower limit changed to 64% on page 10. 3. compensation component values changed to match figure 24 in ?compensation? on page 14. 4. description in ?protections table? on page 12 changed. 5. equation 5 on page 10, 1.21 changed to 1.22. 6. 30a changed to 21a in ?in-rush control and soft-start? on page 10. 7. 28ms changed to 30.5ms in pin descriptions page 3 and ?enable? on page 9. 8. description of isl97672a introduction changed on page 1. 9. pin description changed on page 3. 10. description for vin, ss, temp_shtdwn, temp_hyst, flag_on changed in electrical specification table 11. 8 channel changed to 6 channel in ?pwm boost converter? on page 9 12. description of ?enable? on page 9 changed 13. description of ?switching frequency? on page 9 changed. 14. description of ?5v low dropout regulator? on page 9 changed. 15. description of ?in-rush control and soft-start? on page 10 changed. 16. "overvoltage protection (ovp) and vout" moved to page 11, combined with original "overvoltage protection" section. 17. 2.45v deleted from ?undervoltage lock-out? on page 11. 18. equation 6 on page 12 changed. 19. ?input capacitor? on page 13 changed. 20. ?inductor? on page 13 changed 21. added "note" in "output capacitor" section on page 13 combined "output ripple" section with "output capacitor" section. 22. description of ?schottky diode? on page 13 changed. 23. description of ?compensation? on page 14 changed. 24. figure 19, 20 deleted. 25. stamp on page 1 changed- isl97671a deleted from recommended replacement part. 26. page 2 ordering information table: replaced retired isl97672airz-eval with ISL97672AIRZ-EVALZ july 25, 2012 1. stamped nrnd reco mmended replacement part isl97672b updated figure 12 on page 7 and figure 13 on page 8. 2. added ?boldface limits apply over the operating ju nction temperature range, -40c to +85c? to common conditions of ?electrical specifications? on page 4. 3. added note 9 to page 6. added note 9 reference to ?v headroom20 ? on page 6. 4. added vheadroom33 to electrical specification table on page 6. 5. changed ?flag_on? on page 6 typ from 0.4 to 0.04. added max of 0.12. 6. on page 9 in equations 1 & 2, changed 401.8 to 410.5. 7. on page 13, added "(50ma@vin=12v)" to ?high-current applications?. 8. added figure 24, ?compens ation circuit,? on page 14. april 13, 2011 fn7710.2 changed units from mv to v for ?vrset? on page 5. march 24, 2011 fn7710.1 initial release to web.
isl97672a 16 fn7710.3 november 22, 2013 package outline drawing l20.3x4 20 lead quad flat no-lead plastic package rev 1, 3/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 0.10 m c a b mc 0.05 0.15 0.08 c 0.10 c a b c c 4.00 3.00 20x 0.400.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.07 20x a a 4 (4x) seating plane 0.9 0.10 5 0.2 ref 0.05 max. see detail "x" 0.00 min. (c 0.40) 1 20 17 16 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16x view "a-a" pin 1 index area pin 1 index area 6 6

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